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TDA7580
FM/AM DIGITAL IF SAMPLING PROCESSOR
PRODUCT PREVIEW
s s
s s s s s
FM/AM IF SAMPLING DSP ON-CHIP ANALOGUE TO DIGITAL CONVERTER FOR 10.7MHz IF SIGNAL CONVERSION SOFTWARE BASED CHANNEL EQUALIZATION FM ADJACENT CHANNEL SUPPRESSION RECEPTION ENHANCEMENT IN MULTIPATH CONDITION STEREO DECODER AND WEAK SIGNAL PROCESSING 2 CHANNELS SERIAL AUDIO INTERFACE (SAI) WITH SAMPLE RATE CONVERTER I2C AND BUFFER-SPI CONTROL INTERFACES RDS FILTER, DEMODULATOR & DECODER INTER PROCESSOR TRANSPORT INTERFACE FOR ANTENNA AND TUNER DIVERSITY FRONT-END AGC FEEDBACK
TQFP64 ORDERING NUMBER: TDA7580
DESCRIPTION The TDA7580 is an integrated circuit implementing an advanced mixed analogue and digital solution to perform the signal processing of a AM/FM channel. The HW&SW architecture has been devised so to have a digital equalization of the FM/AM channel; hence a real rejection of adjacent channels and any other signals interfering with the listening of the desired station. In severe Multiple Paths conditions, the reception is improved to get the audio with high quality.
s s s
s
BLOCK DIAGRAM
A/D
RDS
I2C/SPI
I2C/SPI HS3I
IF Digital Signal Processor
SAI1
DAC
SAI0
CGU Oscillator
SRC
July 2002
This is preliminary information on a new product now in development. Details are subject to change without notice.
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TDA7580
DESCRIPTION (continued) The algorithm is self-adaptive, thus it requires no "on-the-field" adjustments after the parameters optimization. The chip embeds a Band Pass Sigma Delta Analogue to Digital Converter for 10.7MHz IF conversion from a "tuner device" (it is highly recommended the TDA7515). The internal 24bit-DSP allows some flexibility in the algorithm implementation, thus giving some freedom for customer required features. The total processing power offers a significant headroom for customer's software requirement, even when the channel equalization and the decoding software is running. The Program and Data Memory space can be loaded from an external non volatile memory via I 2C or SPI. The oscillator module works with an external 74.1MHz quartz crystal. It has very low Electro Magnetic Interference, as it introduces very low distortion, and in any case any harmonics fall outside the Radio bandwidth. The companion tuner device receives the reference clock through a differential ended interface, which works off the Oscillator module by properly dividing down the master clock frequency. That allows the overall system saving an additional crystal for the tuner. After the IF conversion, the digitized baseband signal passes through the Base Band processing section, either FM or AM, depending on the listener selection. The FM Base Band processing comprises of Stereo Decoder, Spike Detection and Noise Blanking. The AM Noise Blanking is fully software implemented. The internal RDS filter, demodulator and decoder features complete functions to have the output data available through either I2C or SPI interface. No DSP support is needed but at start-up, so that RDS can work in background and in parallel with other DSP processing. This mode (RDS-only) allows current consumption saving for low power application modes. An I2C/SPI interface is available for any control and communication with the main micro, as well as RDS data interface. The DSP SPI block embeds a 10 words FIFO for both transmit and receive channels, to lighten the DSP task and frequently respond to the interrupt from the control interface. Serial Audio Interface (SAI) is the ideal solution for the audio data transfer, both transmit and receive: either master or slave. The flexibility of this module gives a wide choice of different protocols, including I2S. Two fully independent bidirectional data channels, with separate clocks allows the use of TDA7580 as general purpose digital audio processor. A fully Asynchronous Sample Rate Converter (ASRC) is available as a peripheral prior to sending audio data out via the SAI, so that internal audio sampling rate (~36kHz and FM/AM mode) can be adapted by upconversion to any external rate. An Inter Processor Transport Interface (HS 3I, High Speed Synchronous Serial Interface) is also available for a modular system which implements Dual Tuner Diversity, thus enhancing the overall system performance. It is about a Synchronous Serial Interface which exchanges data up to the MPX rate. It has been designed to reduce the Electro Magnetic Interference toward the sensitive analogue signal from the Tuner. General Purpose I/O registers are connected to and controlled by the DSP, by means of memory map. A Debug and Test Interface is available for on-chip software debug as well as for internal registers read/write operation.
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ABSOLUTE MAXIMUM RATINGS
Symbol VDD VDD3 Power supplies (1) Parameter Nom. 1.8V Nom. 3.3V Value -0.5 to 2.5 -0.5 to 4.0 -0.5 to 4.0 Unit V V V
Analog Input or Output Voltage belonging to 3.3V IO ring (VDDSD, VDDOSC) Digital Input or Output Voltage, 5V tolerant Normal(2) Fail-safe(3) Nom. 1.8V Nom. 3.3V
-0.5 to 6.50 -0.5 to 3.80 -0.5 to (VDD+0.5) -0.5 to (VDD3+0.5) -40 to 125 -55 to 150
V V V C C
All remaining Digital Input or Output Voltage Tj Tstg Operating Junction Temperature Range Storage Temperature
Warning: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Note: 1. VDD3 refers to all of the nominal 3.3V power supplies (VDDH, VOSC, VDDSD). VDD refers to all of the nominal 1.8V power supplies (VDD, VMTR). 2. During Normal Mode operation VDD3 is always available as specified 3. During Fail-safe Mode operation VDD3 may be not available.
THERMAL DATA
Symbol Rth j-amb Parameter Thermal resistance junction to ambient Value 68 Unit C/W
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TDA7580
PIN CONNECTION (Top view)
DBOUT1
DBOUT0
VDDISO
VDDSD
DBRQ1
DBRQ0
DBCK1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
VHI VCM VLO INP INN VCMOP GNDSD GNDOSC XTI XTO VDDOSC VDDMTR CKREFP CKREFN AGCKEY GNDMTR
49
DBCK0
DBIN1
DBIN0
GNDH
GNDH
VDDH
VDDH
GND
VDD
1 2 3
48 46
GND VDD TST3_LRCKR TST2_SCKR LRCK_LRCKT SCLK_SCKT SDO0 VDDH GNDH TST1_SDI1 TST4_SDI0 GPIO_SDO1 TESTN GND VDD RESETN
DEBUG1 IFADC
DEBUG0 47
45 44 43 42
4 5 6 7 8 10 11 13 14 15 16 17 12
SAI OSC. Tuner
41 40 39 38 37 36 35
9
S D R PI P/ S2 C/S DI
19 20 21 22 23
HS3I
24 25 26 27 28
RDS
29 30 31
INT
34 33 32
ADDR_SD
PROTSEL_SS
18
IQCH1
IQCH2
SCL_SCK
IQSYNC
IQCH3
MISO
VDD
SDA_MOSI
GNDH
GND
IFADC Modulator Power Supply pins pair Oscillator Power Supply pins pair Tuner Clock Out and AGC Keying DAC Power Supply pins pair Core Logic 1.8V Power Supply pins pair I/O Ring 3.3V Power Supply pins pair
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RDS_INT
RDS_CS
VDDH
TDA7580
PIN DESCRIPTION
N 1 VHI Name Type A Description Internally generated IFADC Opamps 2.65V (@VDD=3.3V) Reference Voltage Pin for external filtering Internally generated Common Mode 1.65V (@VDD=3.3V) Reference Voltage Pin for external filtering Internally generated IFADC Opamps 0.65V (@VDD=3.3V) Reference Voltage Pin for external filtering Positive IF signal input from Tuner Negative IF signal input from Tuner Internally generated Modulator Opamps Common Mode 2.65V (@VDD=3.3V) Reference Voltage Pin for external filtering IFADC Modulator Analogue Ground Notes It needs external 22F and 220nF ceramic capacitors It needs external 22F and 220nF ceramic capacitors It needs external 22F and 220nF ceramic capacitors 2.0Vpp @VDD=3.3V 2.0Vpp @VDD=3.3V It needs external 22F and 220nF ceramic capacitors Clean Ground, to be star-connected to voltage regulator ground Clean Ground, to be star-connected to voltage regulator ground Maximum voltage swing is VDD After Reset
2
VCM
A
3
VLO
A
4 5 6
INP INN VCMOP
A A A
7
GNDSD
G
8
GNDOSC
G
Oscillator Ground
9
XTI
I
High impedance oscillator input (quartz connection) or clock input when in Antenna Diversity slave mode Low impedance oscillator output (quartz connection) Oscillator Power Supply Tuner reference clock and AGCKeying DAC Power Supply Tuner reference clock positive output.
10 11 12 13
XTO VDDOSC VDDMTR CKREFP
O P P B
3.3V 1.8V FM 100kHz AMEU 18kHz With internal pull_up, on at reset FM 100kHz AMEU 18kHz With internal pull_up, on at reset 1.5kohm 30% output impedance. 1Vpp 1% output dynamic range Output
14
CKREFN
B
Tuner reference clock negative output.
Output
15
AGCKEY
A
DAC output for Tuner AGCKeying
16
GNDMTR
G
Tuner reference clock and AGC keying DAC Ground
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TDA7580
PIN DESCRIPTION (continued)
N 17 Name PROTSEL_SS Type B Description DSP0 GPIO for Control Serial Interface (Low: SPI or High: I2C) selection at device Bootstrap. In SPI protocol mode, after Boot procedure, SPI Slave Select, otherwise DSP0 GPIO0 Notes DSP0 GPIO0 5V tolerant With internal pull_up, on at reset After Reset Input
18
SDA_MOSI
B
5V tolerant Control Serial Interface and RDS IO: - SPI mode: slave data in or master data With internal pull_up, on at reset out for main SPI and RDS SPI data in - I2C mode: data for main I2C or RDS I2C SPI slave data out or master data in for main SPI and RDS SPI data out DSP0 GPIO1 5V tolerant With internal pull_up, on at reset 5V tolerant With internal pull_up, on at reset
Input
19
MISO
B
Input
20
SCL_SCK
B
Bit clock for Control Serial Interface and RDS Digital Core Power Ground Digital Core Power Supply High Speed Synchronous Serial Interface (HS3I) clock if HS3I master mode, else DSP1 GPIO or DSP1 Debug Port Clock (DBOUT1) High Speed Synchronous Serial Interface (HS3I) Channel 1 Data if HS3I master mode, else DSP1 GPIO or DSP1 Debug Port Request (DBRQ1) High Speed Synchronous Serial Interface (HS3I) Channel 2 Data if HS3I master mode, else DSP1 GPIO or DSP1 Debug Port Data In (DBIN1) High Speed Synchronous Serial Interface (HS3I) Channel 3 Data if HS3I master mode, else DSP1 GPIO or DSP1 Debug Port Data Out (DBCK1) 3.3V IO Ring Power Supply (HS3I, I2C/ SPI, RDS, INT) 3.3V IO Ring Power Ground (HS3I, I2C/ SPI, RDS, INT) RDS interrupt to external main microprocessor in case of traffic information
Input
21 22 23
GND VDD IQSYNC
G P B
1.8V DSP1 GPIO0 5V tolerant With internal pull_up, on at reset DSP1 GPIO1 5V tolerant With internal pull_up, on at reset DSP1 GPIO2 5V tolerant With internal pull_down, on at reset DSP1 GPIO3 5V tolerant With internal pull_down, on at reset Input
24
IQCH1
B
Input
25
IQCH2
B
Input
26
IQCH3
B
Input
27
VDDH
P
28
GNDH
G
29
RDS_INT
B
DSP1 GPIO4 5V tolerant With internal pull_up, on at reset
Input
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TDA7580
PIN DESCRIPTION (continued)
N 30 Name RDS_CS Type B Description RDS chip select. When RESETN rising, If RDS_CS 0, the RDS's SPI is selected; else RDS's I2C DSP0 External Interrupt IFS chip master (Low) or slave (High) mode selection, latched in upon RESETN release. It selects the LSB of the I2C addresses. Station Detector output Chip Hardware reset, active Low Digital Power Supply Digital Power Ground Test Enable pin, active Low DSP0 GPIO for Boot selection or Audio SAI0 output. With internal pull_up 5V tolerant DSP0 GPIO3 With internal pull_up, on at reset 5V tolerant DSP0 GPIO5With internal pull_up, on at reset 5V tolerant DSP0 GPIO4With internal pull_up, on at reset Input Notes DSP1 GPIO5 5V tolerant With internal pull_up, on at reset 5V tolerantWith internal pull_up, on at reset DSP0 GPIO2 5V tolerantWith internal pull_down, on at reset Input After Reset Input
31 32
INT ADDR_SD
I B
33 34 35 36 37
RESETN VDD GND TESTN GPIO_SDO1
I P G I B
5V tolerant With internal pull_up 1.8V
38
TST4_SDI0
B
Audio SAI0 Data input or test selection pin in Test Mode
Input
39
TST1_SDI1
B
DSP0 GPIO for Boot selection or Audio SAI1 input. Test selection pin in Test Mode. 3.3V IO Ring Power Ground (Audio SAI, ResetN, Test Pins) 3.3V IO Ring Power Supply (Audio SAI, ResetN, Test Pins) Radio or Audio SAI0 data output
Input
40 41 42
GNDH VDDH SDO0
G P B
5V tolerant With internal pull_up, on at reset 5V tolerant With internal pull_up, on at reset 5V tolerant With internal pull_up, on at reset
Output
43
SCLK_SCKT
B
SAI0 Receive and Transmit bit clock (master or slave with ASRC); SAI1 Transmit bit clock SAI0 Receive and Transmit LeftRight clock (master or slave with ASRC); SAI1 Transmit LeftRight clock
Input
44
LRCK_LRCKT
B
Input
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TDA7580
PIN DESCRIPTION (continued)
N 45 Name TST2_SCKR Type B Description SAI0 Transmit bit clock; SAI1 Receive and Transmit bit clock. Or Test selection pin in Test Mode SAI0 Transmit LeftRight clock; SAI1 Receive and Transmit bit clock. Or Test selection pin in Test Mode Digital Core Power Supply Digital Core Power Ground Debug Port Clock of DSP0 (DBCK0) DSP0 GPIO9 5V tolerant With internal pull_down, on at reset DSP0 GPIO11 5V tolerant With internal pull_down, on at reset DSP0 GPIO 5V tolerant With internal pull_up, on at reset DSP0 GPIO10 5V tolerant With internal pull_up, on at reset Input Notes 5V tolerant DSP0 GPIO6 With internal pull_up, on at reset DSP0 GPIO7 5V tolerant With internal pull_up, on at reset 1.8V After Reset Input
46
TST3_LRCKR
B
Input
47 48 49
VDD GND DBCK0
P G B
50
DBIN0
B
Debug Port Data Input of DSP0 (DBIN0)
Input
51
DBRQ0
B
Debug Port Request of DSP0 (DBRQ0)
Input
52
DBOUT0
B
Debug Port Data Output of DSP0 (DBOUT0)
Input
53 54 55
GNDH VDDH DBCK1
G P B
3.3V IO Ring Power Ground (Debug Interface, GPIO) 3.3V IO Ring Power Supply (Debug Interface, GPIO) DSP1 Debug Port Clock (DBCK1) if HS3I master mode, else High Speed Synchronous Serial Interface (HS3I) Channel3 Data DSP1 GPIO or DSP1 Debug Port Data In (DBIN1) if HS3I master mode, else High Speed Synchronous Serial Interface (HS3I) Channel2 Data i DSP1 GPIO or DSP1 Debug Port Request (DBRQ1) if HS3I master mode, else High Speed Synchronous Serial Interface (HS3I) Channel1 Data DSP1 GPIO9 5V tolerant With internal pull_down, on at reset DSP1 GPIO11 5V tolerant With internal pull_down, on at reset 5V tolerant With internal pull_up, on at reset Input
56
DBIN1
B
Input
57
DBRQ1
B
Input
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TDA7580
PIN DESCRIPTION (continued)
N 58 Name DBOUT1 Type B Description DSP1 GPIO or DSP1 Debug Port Data Out (DBOUT1) if HS3I master mode, else High Speed Synchronous Serial Interface (HS3I) clock Digital Core Power Supply Digital Core Power Ground 3.3V N-isolation biasing supply Clean 3.3V supply to be star-connected to voltage regulator Notes DSP1 GPIO10 5V tolerant With internal pull_up, on at reset After Reset Input
59 60 61
VDD GND VDDISO
P G P
1.8V
62 63 64
GNDH VDDH VDDSD
G P P
3.3V IO Ring Power Ground (Modulator digital section) 3.3V IO Ring Power Supply (Modulator digital section) 3.3V IFADC Modulator Analogue Power Supply Clean Power Supply, to be star-connected to 3.3V voltage regulator
I/O TYPE P: Power Supply from Voltage regulator G: Power Ground from Voltage regulator A: Analogue I/O I: Digital Input O: Digital Output B: Bidirectional I/O
I/O DEFINITION AND STATUS Z: high impedance (input) O: logic low output X: undefined output 1: logic high output Output PP: Push-Pull/ OD: Open-Drain
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TDA7580
RECOMMENDED DC OPERATING CONDITIONS
Symbol VDD VDDH VOSC VDDSD VMTR Parameter 1.8V Power Supply Voltage 3.3V Power Supply Voltage (1) 3.3V Power Supply Voltage (1) 3.3V Power Supply Voltage (1) 1.8V Power Supply Voltage Comment Core Power Supply IO Rings Power Supply (with GNDH) Oscillator Power Supply (GNDOSC) IF ADC Power Supply (with GNDSD) DAC-Keying and Tuner clock Power Supply (with GNDMTR) Min. 1.7 3.15 3.15 3.15 1.7 Typ. 1.80 3.30 3.30 3.30 1.80 Max. 1.9 3.45 3.45 3.45 1.9 Unit V V V V V
Note: 1. VDDH, VOSC, VDDSD are also indicated in this document as VDD3. All others as VDD.
GENERAL INTERFACE ELECTRICAL CHARACTERISTICS
Symbol lilh lihh lil lih Iipdh Iopuh Iopul Iaihop Parameter Low Level Input Current I/Os@VDD3 (absolute value) High Level Input Current I/Os@VDD3 (absolute value) Low Level Input Current I/Os@VDD (absolute value) High Level Input Current I/Os@VDD (absolute value) Pull-down current I/Os @ VDD3 Pull-up current I/Os @ VDD3 Pull-up current I/Os @ VDD Analogue pin sunk/drawn current on pin1 and pin 6 Analogue pin sunk/drawn current on pin 2 Analogue pin sunk/drawn current on pin 3 Analogue pin sunk/drawn current on pin 4 and pin 5 Analogue pin sunk/drawn current on pin 15 Tri-state Output leakage Test Condition Vi = 0V (notes 1, 2) without pull-up-down device Vi = VDD3 (notes 1, 2) without pull-up-down device Vi = 0V (notes 1, 3, 4) without pull-up-down device Vi = VDD (notes 1, 3, 4) without pull-up device Vi = VDD3 (note 5) with pull-down device Vi = 0V(note 6) with pull-up device Vi = 0V (note 3) with pull-up device Vi = VDD3 Vi = 0V Iacm Vi = VDD3 Vi = 0V Iail Vi = VDD3 Vi = 0V Iain Vi = VDD3 Vi = 0V Iaik Vi = VDD Vi = 0V (spec absolute value) Ioz Vo = 0V or VDD3 (note 1) without pull up/down device 3.2 -10.0 -5.4 0.95 -6.25 1.5 -2.5 3.75 -1.55 24 -40 0.8 6.6 -6.6 -3.6 1.25 -5.0 2.0 -2.0 5.0 -1.25 32 -32 1.2 Min. Typ. Max. 1 1 1 1 10.0 -3.2 -1.8 1.55 -3.75 2.5 -1.5 6.25 -0.95 40 -24 1.6 1 1 Unit A A A A A A A mA mA mA mA mA mA A A mA A A
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TDA7580
GENERAL INTERFACE ELECTRICAL CHARACTERISTICS (continued)
Symbol IozFT Parameter 5V Tolerant Tri-state Output leakage (without pull up/down device) I/O latch-up current Electrostatic Protection Test Condition Vo = 0V or Vdd (note 1) Vo = 5.5V V < 0V, V > Vdd Leakage, 1A 200 2000 1 Min. Typ. Max. 1 3 Unit A A mA V
Ilatchup Vesd
Note: 1. The leakage currents are generally very small, <1nA. The value given here, 1A, is the maximum that can occur after an Electrostatic Stress on the pin. 2. On pins:17 to 20,23 to 26,29 to 33,36 to 39,42 to 46,49 to 52,55 to 58. 3. On pins: 13 and 14. 4. Same check on the analogue pin 15 (phisically without pull-up-down) 5. On pins:25, 26,32,49,50,55,56 6. On pins:17 to 20,23 to 24,29 to 31,33,36 to 39,42 to 46,51, 52,57, 58
LOW VOLTAGE CMOS INTERFACE DC ELECTRICAL CHARACTERISTICS
Symbol Vil Vih Vol Voh Parameter Low Level Input Voltage High Level Input Voltage Low level output Voltage High level output Voltage Test Condition 1.70V<=VDD<=1.90V 1.70V<=VDD<=1.90V Iol = 4mA (notes 1) I ol = -4mA (notes 1) VDD-0,15 0.8*VDD3 0.15 Min. Typ. Max. 0.3*VDD3 Unit V V V V
Note: 1. It is the source/sink current under worst case conditions and reflects the name of the I/O cell according to the drive capability.
HIGH VOLTAGE CMOS INTERFACE DC ELECTRICAL CHARACTERISTICS
Symbol Vil Vih Vol Voh Parameter Low Level Input Voltage High Level Input Voltage Low level output Voltage High level output Voltage Test Condition 3.15V<=VDD3<=3.45V 3.15V<=VDD3<=3.45V Iol = XmA (notes 1 and 2) I ol = -XmA (notes 1 and 2) VDD3-0.15 2.0 0.15 Min. Typ. Max. 0.8 Unit V V V V
Note: 1. It is the source/sink current under worst case conditions and reflects the name of the I/O cell according to the drive capability 2. X=4mA for pins 17 to 20,29,30,32,36 to 39,42 to 46; X=8mA for pins 23 to 26,49 to 52,55 to 58.
CURRENT CONSUMPTION
Symbol IDD IDDH ISD IOSCdc Parameter Current through VDD Power Supply Current through VDDH Power Supply Current through VSD Power Supply Current through VOSC Power Supply Test Condition VDD=1.8V,VDD3=3.3V All digital blocks working VDD=1.8V,VDD3=3.3V All I/Os working with 5pF load VDD=1.8V,VDD3=3.3V VDD=1.8V,VDD3=3.3V without quartz 36 5.5 Min. Typ. 120 3 45 8 Max. 200 5 54 10.5 Unit mA mA mA mA
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TDA7580
CURRENT CONSUMPTION (continued)
Symbol IOSCac IMTR Parameter Current through VOSC Power Supply Current through VMTR Power Supply Test Condition VDD=1.8V,VDD3=3.3V with quartz in FM mode VDD=1.8V,VDD3=3.3V Min. 11 Typ. 14 5 Max. 17 Unit mA mA
Note: 74.1MHz internal DSP clock, at Tamb = 25C. Current due to external loads not included.
OSCILLATOR CHARACTERISTICS
Symbol FOSCFM FOSCAM Parameter Oscillator Frequency (XTI/XTO) Oscillator Frequency (XTI/XTO) Test Condition VOSC @ 3.3V VOSC @ 3.3V Min. Typ. 74.1 74.106 Max. Unit MHz MHz
Notes: 1. The accuracy of this figure only depends on the quartz frequency precision: high stability oscillator
QUARTZ CHARACTERISTICS
Parameter Name Temperature range Adjustment tolerance (@ 25C 3C) Frequency stability (-20C / +70C) Aging @ 25C Shunt (static) capacitance (Co) Packages (holders) Mode of oscillation Resonance resistance (ESR) Oscillation Frequency (without external load) Oscillation Frequency (12pF parallel load) Parameter Value -55C / +125C +/-20ppm +/-50ppm 5ppm/year <6pF UM-1; HC-52U; HC-35; HC-48U; HC-49U; HC-50U; HC-51U AT-3rd <35ohm 74108000 Hz target 74.1MHz
DSP CORE
Symbol FdspMax Parameter Maximum DSP clock frequency Test Condition At 1.7V Core Power Supply and 125C junction temperature Min. 81.5 Typ. Max. Unit MHz
FM STEREO DECODER CHARACTERISTICS
Symbol a_ch THD (S+N)/N Parameter Channel Separation Total Harmonic Distortion Signal plus Noise to Noise ratio Test Condition Min. 50 0.02 80 Typ. Max. Unit dB % dB
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TDA7580
SAMPLE RATE CONVERTER MCK = 18.525MHz, Fsin/Fsout = 0.820445366
Symbol THD+N Parameter Total Harmonic Distortion + Noise Test Condition 20Hz to 20kHz, Full Scale, 16 bit inp. 20Hz to 20kHz, Full Scale, 20 bit inp. 1 kHz 10 kHz 1 kHz 10 kHz DR IPD fc Rp Rs Tg Fratio Dynamic Range Interchannel Phase Deviation Cutoff Frequency Pass Band Ripple Stopband Attenuation Group Delay Sampling Frequency In/Out Ratio @ -3 dB from 0 to 20kHz @24.1kHz Fsout = 44.1 kHz Fsout = 44.1 kHz 0.7 -0.01 -120 540 1.05 0.01 Full Scale, 16 bit inp. Full Scale, 16 bit inp. Full Scale, 20 bit inp. Full Scale, 20 bit inp Min. Typ. -95 -98 -95 -95 -105 -98 98 120 0 Max. Unit dB dB dB dB dB dB dB dB Degree Hz dB dB s
1 kHz -60 dB - 16 bit inp.,A-Weighted 1 kHz -60 dB - 20 bit inp.,A-Weighted
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TDA7580
POWER ON TIMING Figure 1. Power on and boot sequence using I2C VDD3 VDD INT RESETN ADDR_SD PROTSEL_SS RDS_CS GPIO_SDO1 TST1_SDI1 SDA_MOSI tint trsu treson Figure 2. Power on and boot sequence using SPI VDD3 VDD INT RESETN ADDR_SD PROTSEL_SS RDS_CS GPIO_SDO1 TST1_SDI1 SDA_MOSI tint trsu treson tseq ttun trhd
I2C/SPI SLAVE=1 I2C/SPI MASTER=0 IFS SLAVE=1 IFS MASTER=0 I2C/SPI SLAVE=1 I2C/SPI MASTER=0 IFS SLAVE=1 IFS MASTER=0
Boot
RDS init
SW download
Tuner data
Data
trhd
tsw
tdat
tseq
ttun
Boot
RDS init
SW download
Tuner data
Data
tsw
tdat
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TDA7580
Timing tint treson trsu trhd tseq tsw ttun tdat Description Maximux delay for INT signal Minimum RESETN hold time at 0 after the start-up Minimum data set-up time Minimum data hold time Minimum wait time after boot Minimum wait time before downloading the Program Software Minimum wait time before downloading the software to the FE Minimum wait time before using interface protocols Value 1 22 1 1 4 1 1 1 Unit ms ms s s ms s s s
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TDA7580
SAI INTERFACE
Figure 3. SAI Timings
SDI0-1
Valid
LRCKR
Valid
SCKR
(RCKP=0)
tlrs tdt tsckpl tsdis
tlrh tsdih tsckph tsckr
Timing TDSP tsckr tdt tlrs tlrh tsdid tsdih tsckph tsckpl
Description Internal DSP Clock Period (Typical 1/74.1MHz) Minimum Clock Cycle SCKR active edge to data out valid LRCK setup time LRCK hold time SDI setup time SDI hold time Minimum SCK high time Minimum SCK low time
Value 13.495 32*TDSP 40 16 9 16 9 0.5*tsckr 0.5*tsckr
Unit ns ns ns ns ns ns ns ns ns
Note T DSP = DSP master clock cycle time = 1/FDSP
Figure 4. SAI protocol when RLRS=0; RREL=0; RCKP=1; RDIR=0
LRCKR SCKR
LEFT
RIGHT
SDI0-1
LSB(n-1)
MSB(n)
MSB-1(n)
MSB-2(n)
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TDA7580
Figure 5. SAI protocol when RLRS=1; RREL=0; RCKP=1; RDIR=1.
LRCKR SCKR
LEFT
RIGHT
SDI0-1
MSB(n-1)
LSB(n)
LSB+1(n)
LSB+2(n)
Figure 6. SAI protocol when RLRS=0; RREL=0; RCKP=0; RDIR=0.
LRCKR
SCKR
LEFT
RIGHT
SDI0-1
LSB(n-1)
MSB(n)
MSB-1(n)
MSB-2(n)
Figure 7. SAI protocol when RLRS=0; RREL=1; RCKP=1; RDIR=0.
LRCKR
SCKR
LEFT
RIGHT
SDI0-1
LSB(n-1)
MSB(n)
MSB-1(n)
MSB-2(n)
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TDA7580
SPI INTERFACE
Figure 8. SPI Timings
SS
Valid
MISO MOSI
Valid
SCL
(CPOL=0,CPHA=0)
tsetup tdtr tsclkl tsssetup
thold tsshold tsclkh tsclk
Symbol TDSP
Description Internal DSP Clock Period (Typical 1/74.1MHz) MASTER
Value 13.495
Unit ns
tsclk tdtr tsetup thold tsclkh tsclkl tsssetup tsshold
Minimum Clock Cycle Minimum Sclk edge to MOSI valid Minimum MISO setup time Minimum MISO hold time Minimum SCK high time Minimum SCK low time Minimum SS setup time Minimum SS hold time SLAVE
12*TDSP 40 16 9 0.5*tsclk 0.5*tsclk 40 25
ns ns ns ns ns ns ns ns
tsclk tdtr tsetup thold tsclkh
Minimum Clock Cycle Minimum Sclk edge to MOSI valid Minimum MOSI setup time Minimum MOSI hold time Minimum SCK high time
12*TDSP 40 16 9 0.5*tsclk
ns ns ns ns ns
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TDA7580
Symbol tsclkl tsssetup tsshold Minimum SCK high low Minimum SS setup time Minimum SS hold time Description Value 0.5*tsclk 40 20 Unit ns ns ns
Figure 9. SPI Clocking Scheme
SS(#17)
(CPOL=0,CPHA=0)
SCK(#20)
SCK(#20) SCK(#20)
(CPOL=0,CPHA=1)
(CPOL=1,CPHA=0)
SCK(#20)
(CPOL=1,CPHA=1)
MISO(#19) MOSI(#18)
MSB
6
5
4
3
2
1
0
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TDA7580
INTER PROCESSOR TRANSPORT INTERFACE FOR ANTENNA DIVERSITY Figure 10. High Speed Synchronous Serial Interface - HS3I
Master Bit Clock
Master Data Out
M2
M3 256 cycles of 74.1MHz
Master Synch
Slave Data Out
S0
S1
S2
S3
tmbcc tmbco tmbcs tsdos
Master Bit Clock
Master Data Out
Master Synch
Slave Data Out
Timing TDSP tmbcc tmbco tmbcs tsdos
Description Internal DSP Clock Period (Typical 1/74.1MHz) MBC minimum Clock Cycle MBC active edge to master data out valid MBC active edge to master synch valid Slave Data Out setup time
Value
Unit
32*TDSP 4 4 6
ns ns ns ns
Note T DSP = DSP master clock cycle time = 1/FDSP
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TDA7580
I2C TIMING Figure 11. DSP and RDS I2C BUS Timings.
Symbol
Parameter
Test Condition
Standard Mode I2C BUS Min. Max. 100 - -
Fast Mode I2C BUS Min. 0 1.3 0.6 Max. 400 - -
Unit
FSCL tBUF tHD:STA
SCLl clock frequency Bus free between a STOP and Start Condition Hold time (repeated) START condition. After this period, the first clock pulse is generated LOW period of the SCL clock HIGH period of the SCL clock Set-up time for a repeated start condition DATA hold time Rise time of both SDA and SCL signals Fall time of both SDA and SCL signals Set-up time for STOP condition Data set-up time Capacitive load for each bus line Cb in pF Cb in pF
0 4.7 4.0
kHz s s
tLOW tHIGH tSU:STA tHD:DAT tR tF tSU;STO tSU:DAT Cb
4.7 4.0 4.7 0 - - 4 250 -
- - - - 1000 300 - -400
1.3 0.6 0.6 0 20+ 0.1Cb 20+ 0.1Cb 0.6 --
- - - 0.9 300 300 - 100 400
s s s s ns ns s ns pF
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TDA7580
FUNCTIONAL DESCRIPTION The TDA7580 IC is a complete solution for high performance FM/AM Car Radio receivers, and has high processing power to allow Audio processing of both internal and external Audio source. The processing engine is made of programmable DSP, with separate banks of Program and Data RAMs. In addition a number of hardware modules (peripherals) which help in the algorithm implementation of channel equalization, and FM/AM Baseband post-processing. The HW architecture allows to perform Dual Tuner Diversity. In this case two TDA7580 are needed: one device must be configurated as Master, generates the clock and controls the main data interfaces. The second device becomes Slave and converts the second IF path, as well as helps the first chip as co-processor. 24-BIT DSP CORE Some capabilities of the DSP are listed below: s Single cycle multiply and accumulate with convergent rounding and condition code generation s 24 x 24 to 56-bit MAC Unit s Double precision multiply s Scaling and saturation arithmetic s 48-bit or 2 x 24-bit parallel moves s 64 interrupt vector locations s Fast or long interrupts possible s Programmable interrupt priorities and masking s Repeat instruction and zero overhead DO loops s Hardware stack capable of nesting combinations of 7 DO loops or 15 interrupts/subroutines s Bit manipulation instructions possible on all registers and memory locations, also Jump on bit test s 4 pin serial debug interface s Debug access to all internal registers, buses and memory locations s 5 word deep program address history FIFO s Hardware and software breakpoints for both program and data memory accesses s Debug Single stepping, Instruction injection and Disassembly of program memory DSP PERIPHERALS s Clock Generation Unit (CGU) s Stereo Decoder (HWSTER) s Serial Audio Interface (SAI) s Tuner AGC Keying DAC (KEYDAC) s Programmable I/O Interface (I2C/BSPI) s Asynchronous Sample Rate Converter (ASRC) s IF Band Pass Sigma Delta Modulator (IFADC) s Digital Down Converter (DDC) s Discriminator (CORDIC) s RDS 3 s Tuner Diversity HS I
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TDA7580
DSP PERIPHERALS The peripherals are mapped in the X-memory space. Most of them can be handled by interrupt, with software programmable priority. Peripherals running at very high rate have direct access to X and Y Data Bus for very fast movement from or to the core, by mean of single cycle instruction. CLOCK GENERATION UNIT (CGU) and OSCILLATOR This unit is responsible for supplying all necessary clocks and synchronization signals to the whole chip. The control status register of this unit contains information about the current working mode (FM,AM,oscillator [master mode] or clock buffer [slave mode]), the tuner clock frequency setting, the general setup of the oscillator. This last function is performed inside the CGU, that establishes -using a self-trimming algorithm- which is the current that can bias the oscillator: this feature let the oscillator be independent from process parameters variation. The values of bias current are stored in the control status register of the CGU: 4 bit for the coarse current steps and 6 bit for the fine current steps. The bits relative to the fine current steps can be anyway corrected (written) by the DSP to perform the SW frequency trimming (+/-80Hz per step in FM; +/-250Hz in AM). It sets up the oscillator which works off a quartz crystal of nominally 74.1MHz, generating very low distortion, thus improving the Electro Magnetic Interference. In FM mode the oscillator generates 74.1MHz, meanwhile in AM mode this frequency is shifted to 74.106MHz. The quartz characteristics are defined earlier in this document. In Slave mode the oscillator behaves as a buffer: the chip can be then driven using an external clock. The clock divider, placed in this unit, gives the tuner the reference clock (100KHz in FM and AMUS, 18KHz in AMEU). STEREO DECODER (HWSTER) The fully digital hardware stereo decoder does all the signal processing necessary to demodulate an FM MPX signal which is prepared by the channel equalization algorithm in the digital IF sampling device. It makes up of pilot tone dependent Mono/Stereo switching as well as stereoblend and highcut. Selectable deemphasis time constant allow the use of this module for different FM radio receiver standards. There are built-in filters for field strength processing. In order to obtain the maximum flexibility the field strength processing and noise cancellation, however, are implemented as software inside the programming DSP, which has to provide control signals for the stages softmute, stereoblend, and highcut. SERIAL AUDIO INTERFACE (SAI) The two SAI modules have been embedded in such a way great flexibility is available in their use. The two modules are fully separate and they each have a Receive and a Transmit channel, as well as they can be selected as either master or slave. The bit clocks and Left&Right clocks are routed through the pins, so the audio interface can be chosen to be adapted to a large variety of application. One SAI transmit channel can have the Asynchronous Sample Rate Converter in front, thus separate different audio rate domains. Additional feature are: s support of 16/24/32 bit word length
s s s
programmable left/right clock polarity programmable rising/falling edge of the bit clock for data valid programmable data shift direction, MSB or LSB received/transmitted first
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TDA7580
I2C INTERFACES The inter Integrated Circuit bus is a single bidirectional two-wire bus used for efficient inter IC control. All I2C bus compatible devices incorporate an on-chip interface which allows them communicate directly with each other via the I2C bus. Every component hooked up to the I 2C bus has its own unique address whether it is a CPU, memory or some other complex function chip. Each of these chips can act as a receiver and /or transmitter on its functionality. Two pins are used to interface both I2C of the DSP and RDS, which have different internal I2C address, thus reducing the on-board pin interconnections. SERIAL PERIPHERAL INTERFACES The DSP and RDS can have this serial interface, alternative to the I2C one. DSP and RDS SPI modules have separate pin for chip select. The DSP SPI has a ten 24bit-words deep FIFO for both receive and transmit sections, which reduces DSP processing overhead even at high data rate. The serial interface is needed to exchange commands and data over the LAN. During an SPI transfer, data is transmitted and received simultaneously. A serial clock line synchronizes shifting and sampling of the information on the two serial data lines. A slave select line allows individual selection of a slave SPI device. When an SPI transfer occurs an 8-bit word is shifted out one data pin while another 8-bit character is simultaneously shifted in a second data pin.The central element in the SPI system is the shift register and the read data buffer. The system is single buffered in the transfer direction and double buffered in the receive direction. HIGH SPEED SERIAL SYNCHRONOUS INTERFACE (HS3I) The High Speed Serial Synchronous Interface is a module to send and receive data at high rate (up to 9.25Mbit/ s per channel) in order to exchange data between 2 separate TDA7580 chip. The exchanged data are related to signals that are used to increase reception quality in Car Radio systems, which make use of Antenna Diversity based upon two separate antenna and tuner sections. The channel synchronization clock has a programmable duty cycle, so to reduce in-band harmonics noise. TUNER AGC KEYING DAC (KEYDAC) This DAC provides the front-end tuner with an analogue signal to be used to control the Automatic Gain Controlled stage, thus giving all time the best voltage dynamic range at the IFADC input. ASYNCHRONOUS SAMPLE RATE CONVERTER (ASRC) This hardware module provides a very flexible way to adapt the internal audio rate, to the one of an external source. It does not require further work off the DSP. There is no need to explicitly configure the input and the output sample rates, as the ASRC solves this problem with an automatic Digital Ratio Locked Loop. Main features are: s Automatic Tracking of Sample Frequency
s s s s
Fully Digital Ratio Locked Loop Sampling Clock Jitter Rejection Up-conversion up to 1:2 Ratio Linear Phase
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TDA7580
IF BAND PASS SIGMA DELTA ANALOGUE TO DIGITAL CONVERTER (IFADC) The IFADC is a Band Pass Sigma Delta A to D converter with sampling rate of 37.05MHz (nominal) and notch frequency of 10.7MHz. The structure is a second order switched capacitor multi bit modulator with self calibration algorithm to adjust the notch frequency. The differential ended input allows 4.0Vpp voltage dynamic range, and reduces the inferred noise back to the previous stage (tuner), and in turn gives high rejection to common mode noises. The high linearity (very high IMD) is needed to fulfill good response of the channel equalization algorithm. Low thermal and 1/f noise assures high dynamic range. DIGITAL DOWN CONVERTER (DDC) The DDC module allows to evaluate the in-phase and quadrature components of the incoming digital IF signal. The I and Q computation is performed by the DDC block, which at the same time shifts down to 0-IF frequency the incoming digital signal. After the down conversion the rate is still very high (at the 37.05MHz rate); a SincK filter samples data down by a factor of 32, decreasing it to 1.1578MHz. An additional decimation is performed by the subsequent FIR filters, thus lowering the data rate at the final 289.45kHz, being the MPX data rate. RDS The RDS block is an hardware cell able to process RDS/RBDS signal, intended for recovering the inaudible RDS/RBDS information which are transmitted by most of FM radio broadcasting stations. It comprises of the following: s Demodulation of the European Radio Data System (RDS)
s s s s s
Demodulation of the US Radio Broadcast Data System (RDBS) Automatic Group and Block synchronisation with flywheel mechanism Error Detection and Correction RAM buffer with a storage capacity of 24 RDS blocks and related status information I2C and SPI interface, with pins shared with the DSP I2C/SPI
After filtering the oversampled MPX signal, the RDS/RDBS demodulator extracts the RDS Data Clock, RDS Data signal and the Quality information. The following RDS/RBDS decoder synchronizes the bitwise RDS stream to a group and block wise information. This processing also includes error detection and error correction algorithms. In addition, an automatic flywheel control avoids exhausting data exchange between RDS/RDBS processor and the host.
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TDA7580
APPLICATION DIAGRAM Hereafter are some examples of Applications in which the TDA7580 can be used. They are just basic references as the device can operate. Figure 12. Radio Mode with external Slave Audio DAC
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
TST3_LRCKR 46 TST2_SCKR 45 LRCK_LRCKT 44 SCLK_SCKT 43 SDO0 42
1 8 7 6 5
49
48 47
TDA7580
41 40
Fs=36kHz
2 3 4
TST1_SDI1 39 TST4_SDI0 38 GPIO_SDO1 37
36 35 34 33 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
TDA7535
Dual DAC
In this mode an external Slave Stereo DAC, like the ST TDA7535, can be easily connected and the TDA7580 outputs the Audio from Radio station at 36kHz rate.
Figure 13. Radio Mode with external Master Audio Device
64
17
63
62
61
60
59
58
57
56
55
54
53
52
51
50
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
TST3_LRCKR TST2_SCKR LRCK_LRCKT SCLK_SCKT SDO0
49
48 47 46
45 44 43 42 41 40 1 2 3
TDA7580
Fs
4
TST1_SDI1 39 TST4_SDI0 38 GPIO_SDO1 37
36 35 34 33 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
External Audio Receiver with its owned audio rate Fs
An external digital Audio device is connected externally as a digital audio master, and the internal TDA7580 Sample Rate Converter is responsible for the conversion from internal 36kHz to the external Audio Rate.
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17
TDA7580
Figure 14. Audio Mode with external Slave Audio Device
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
49
48 47
TST3_LRCKR 46 TST2_SCKR LRCK_LRCKT SCLK_SCKT SDO0
45 44 43 42 41 40 1 2 3 4 1 2 3 4
CD Player Fs=44.1kHz
8 7 6 5 8 7 6 5
TDA7580
TST1_SDI1 39 TST4_SDI0 38 GPIO_SDO1 37
36 35 34 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
Fs=44.1kHz
TDA7535
17
16
Analog In ADC
The 2 stereo channel Serial Audio Interface of the TDA7580 chip allows a very flexible application in which external Audio Source/Sinks can be connected. The example shows an external CD player digital output giving the main Fs audio rate of the whole system. This rate is also the one of the external DACs and an ADC, being configured as slave.
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TDA7580
ELECTRICAL APPLICATION SCHEME The following application diagram must be considered an example. For the real application set-up refers the application notes are necessary .
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TDA7580
PACKAGE MARKING
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TDA7580
DIM. MIN. A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0.40 0.05 1.35 0.18 0.12
mm TYP. MAX. 1.60 0.15 1.40 0.23 0.16 12.00 10.00 7.50 0.50 12.00 10.00 7.50 0.60 1.00 0(min.), 7(max.) 0.75 1.45 0.28 0.20 0.002 0.053 0.007 MIN.
inch TYP. MAX. 0.063 0.006 0.055 0.009 0.057 0.011
OUTLINE AND MECHANICAL DATA
0.0047 0.0063 0.0079 0.472 0.394 0.295 0.0197 0.472 0.394 0.295 0.0157 0.0236 0.0295 0.0393
TQFP64
D D1 A D3 A1 48 49 33 32
0.10mm Seating Plane
A2
B
E3
E1
64 1 e 16
17 C
L1
E
L
K
TQFP64
30/31
B
TDA7580
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (R) 2002 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com
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